In many applications, including clock recovery applications, it is often necessary to compare and control the phase of one or more clock signals. For example, in one common type of analog Clock and Data Recovery system (CDR), the phase of the input data is compared to the phase of two or more sampling clocks. The sampling clocks may be generated, for example, from a fixed reference clock by a Delay-Locked-Loop (DLL). A DLL is a control loop, separate from the primary CDR control loop, that acts to control the spacing between the sampling clocks. The DLL develops a set of phases that are “selected” and interpolated by the CDR control loop to obtain the correct phase required to match-up with the incoming data transition phase.
Typically, a phase detector in the DLL determines the phase difference between adjacent rising edges of two delayed clock signals. If the phase detector detects a phase lag between the rising edges, the phase detector generates a downward control signal, indicating an extent of the phase lag. Likewise, if the phase detector detects a phase lead between the rising edges, the phase detector generates an upward control signal, indicating an extent of the phase lead. The upward and downward control signals are typically applied to a charge pump that generates a positive or negative current pulse having a pulse width that is proportional to the phase difference. Thereafter, the current pulse generated by the charge pump is typically integrated by a loop filter, such as a capacitor. The capacitor voltage is then applied to a bias voltage generator which provides the Voltage Controlled Delay Loop (VCDL) control voltages. The VCDL control voltages then change to raise or lower the delay of each delay cell within the VCDL.
The charge pump and integration capacitor require large area, contributing to the size of any integrated circuit incorporating such a DLL circuit. In addition, since the pulse width of the current generated by the charge pump is proportional to the phase difference, the pulse width must get progressively smaller as the phase difference is reduced. In practice, however, the generation of such small current pulses is difficult and often will result in imperfect linearity as the phase difference approaches zero (0).
A number of techniques have been proposed or suggested for maintaining loop stability and reducing the size of DLL circuits. For example, one proposed technique avoids narrow current pulses by employing a bang-bang phase detector. Another proposed technique replaces the charge-pump and integration capacitor with a digital-accumulator/digital-to-analog converter combination. Another proposed technique uses a smaller digital-accumulator in conjunction with a Sigma-Delta converter/Master-Slave digital-to-analog converter combination.
A need therefore exists for improved techniques for controlling the phase or delay in an analog delay line. A further need exists for an improved delay control circuit for a DLL that exhibits reduced area requirements.